LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY move IS
PORT(
     a,b:in std_logic_vector(3 downto 0);
     s:out std_logic_vector(7 downto 0));
END move;
ARCHITECTURE move_4 OF move IS
SIGNAL temp1,temp2,temp3,temp4:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
  process(a,b,temp1,temp2,temp3,temp4)
    BEGIN
      IF b(0)='1' THEN
         temp1<="0000" & a;
      ELSE
         temp1<="00000000";
      END IF;
      IF b(1)='1' THEN
         temp2<="000" & a & '0';
      ELSE
         temp2<="00000000";
      END IF;
      IF b(2)='1' THEN
         temp3<="00" & a & "00";
      ELSE 
         temp3<="00000000";
      END IF;
      IF b(3)='1' THEN
         temp4<='0' & a & "000";
      ELSE 
         temp4<="00000000";
      END IF;
      s<=temp1 or temp2 or temp3 or temp4;
  END process;
END move_4;  





